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ispgal?22v10av/b/c device datasheet june 2010 all devices discontinued! product change notification (pcn) #09-10 has been issued to discontinue all devices in this data sheet. the original datasheet pages have not been modified and do not reflect those changes. please refer to the table below for refe rence pcn and current product status. product line ordering part number product status reference pcn ispgal22v10av-23ls ispgal22v10av-23lsn ispgal22v10av-5ls ispgal22v10av-5lsn ispgal22v10av-75ls ispgal22v10av-75lsn ispgal22v10av-5lsi ispgal22v10av-5lsni ispgal22v10av-75lsi ispgal22v10av-75lsni ispgal22v10av-28lj ispgal22v10av-5lj ispgal22v10av-75lj ispgal22v10av-5lji ispgal22v10av ispgal22v10av-75lji discontinued pcn#09-10 ispgal22v10ab-23ls ispgal22v10ab-5ls ispgal22v10ab-75ls ispgal22v10ab-5lsi ispgal22v10ab-75lsi ispgal22v10ab-28lj ispgal22v10ab-5lj ispgal22v10ab-75lj ispgal22v10ab-5lji ispgal22v10ab ispgal22v10ab-75lji discontinued pcn#09-10 5555 n.e. moore ct. z hillsboro, oregon 97124-6421 z phone (503) 268-8000 z fax (503) 268-8347 internet: http://www.latticesemi.com
product line ordering part number product status reference pcn ispgal22v10ac-23ls ispgal22v10ac-5ls ispgal22v10ac-75ls ispgal22v10ac-5lsi ispgal22v10ac-75lsi ispgal22v10ac-28lj ispgal22v10ac-5lj ispgal22v10ac-75lj ispgal22v10ac-5lji ispgal22v10ac ispgal22v10ac-75lji discontinued pcn#09-10 5555 n.e. moore ct. z hillsboro, oregon 97124-6421 z phone (503) 268-8000 z fax (503) 268-8347 internet: http://www.latticesemi.com
world's fastest & smallest spld www.latticesemi.com 1 isp22v10a_03.0 ispgal22v10av/b/c in-system programmable low voltage e 2 cmos pld generic array logic december 2008 data sheet ?2008 lattice semiconductor corp. all lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. all other brand or product names are trademarks or registered trademarks of their respective holders. the speci?ations and information herein are subject to change without notice. features high performance ? pd = 2.3ns propagation delay ? max = 455 mhz maximum operating frequency ? co = 2ns maximum from clock input to data output ? su = 1.3 ns clock set-up time low power 1.8v core e 2 cmos technology typical standby power <300? (ispgal22v10ac) cmos design techniques provide low static and dynamic power space-saving packaging available in 32-pin qfns (q uad f lat-pack, n o lead, s aw-singulated) package 5mm x 5mm body size 1 easy system integration operation with 3.3v (ispgal22v10av), 2.5v (ispgal22v10ab) or 1.8v (ispgal22v10ac) supplies operation with 3.3v, 2.5v or 1.8v lvcmos i/o 5v tolerant i/o for lvcmos 3.3 interface hot-socketing open-drain capability input pull-up, pull-down or bus-keeper lead-free package option programmable output slew rate 3.3v pci compatible in-system programmable ieee 1149.1 boundary scan testable 3.3v/2.5v/1.8v in-system programmable (isp) using ieee 1532 compliant interface e 2 cell technology in-system programmable logic 100% tested/100% yields high speed electrical erasure (<50ms) applications include dma control state machine control high speed graphics processing software-driven hardware con?uration boundary scan usercode register supports electronic signature 1. use 32-pin qfns package for all new designs. refer to pcn #13a-08 for 32-pin qfn package discontinuance. introduction the ispgal22v10a is manufactured using lattice semiconductors advanced e 2 cmos process, which combines cmos with electrically erasable (e 2 ) ?ating gate technology. with an advanced e 2 low-power cell and full cmos logic approach, the ispgal22v10a fam- ily offers fast pin-to-pin speeds, while simultaneously delivering low standby power without requiring any ?urbo bits or other traditional power management schemes. the ispgal22v10a can interface with both 3.3v, 2.5v and 1.8v signal levels. the ispgal22v10a is functionally compatible with the ispgal22lv10, gal22lv10 and gal22v10. figure 1. functional block diagram programmable and-array (132x44) i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o tdo tdi tms tck i/clk i i i i i i i i i i reset preset 8 10 12 14 16 16 14 12 10 8 olmc olmc olmc olmc olmc olmc olmc olmc olmc olmc programming logic i all devices discontinued
lattice semiconductor ispgal22v10av/b/c data sheet 2 ispgal architecture output logic macrocell (olmc) the ispgal22v10a has a variable number of product terms per olmc. of the ten available olmcs, two olmcs have access to eight product terms (pins 17 and 27), two have ten product terms (pins 18 and 26), two have twelve product terms (pins 19 and 25), two have fourteen product terms (pins 20 and 24), and two olmcs have sixteen product terms (pins 21 and 23). in addition to the product terms available for logic, each olmc has an additional product-term dedicated to output enable control. the output polarity of each olmc can be individually programmed to be true or inverting, in either combinatorial or registered mode. this allows each output to be individually con?ured as either active high or active low. the ispgal22v10a has a product term for asynchronous reset (ar) and a product term for synchronous preset (sp). these two product terms are common to all registered olmcs. the asynchronous reset sets all registers to zero any time this dedicated product term is asserted. the synchronous preset sets all registers to a logic one on the rising edge of the next clock pulse after this product term is asserted. note: the ar and sp product terms will force the q output of the ?p-?p into the same state regardless of the polarity of the output. therefore, a reset operation, which sets the register output to a zero, may result in either a high or low at the output pin, depending on the pin polarity chosen. figure 2. output logic macrocell output logic macrocell con?urations each of the macrocells of the ispgal22v10a has two primary functional modes: registered, and combinatorial i/o. the modes and the output polarity are set by two bits (s0 and s1), which are normally controlled by the logic com- piler. each of these two primary modes, and the bit settings required to enable them, are described below and on the following page. registered in registered mode the output pin associated with an individual olmc is driven by the q output of that olmcs d- type ?p-?p. logic polarity of the output signal at the pin may be selected by specifying that the output buffer drive either true (active high) or inverted (active low). output tri-state control is available as an individual product-term for each olmc, and can therefore be de?ed by a logic equation. the d ?p-?ps /q output is fed back into the and array, with both the true and complement of the feedback available as inputs to the and array. ar sp d q q clk 4 to 1 mux 2 to 1 mux all devices discontinued
lattice semiconductor ispgal22v10av/b/c data sheet 3 note: in registered mode, the feedback is from the /q output of the register, and not from the pin; therefore, a pin de?ed as registered is an output only, and cannot be used for dynamic i/o, as can the combinatorial pins. combinatorial i/o in combinatorial mode the pin associated with an individual olmc is driven by the output of the sum term gate. logic polarity of the output signal at the pin may be selected by specifying that the output buffer drive either true (active high) or inverted (active low). output tri-state control is available as an individual product-term for each out- put, and may be individually set by the compiler as either ?n (dedicated output), ?ff (dedicated input), or ?rod- uct-term driven (dynamic i/o). feedback into the and array is from the pin side of the output enable buffer. both polarities (true and inverted) of the pin are fed back into the and array. figure 3. registered mode figure 4. combinatorial mode active high active low s 0 = 0 s 1 = 0 s 0 = 1 s 1 = 0 ar sp d q q clk ar sp d q q clk active high active low s 0 = 1 s 1 = 1 s 0 = 0 s 1 = 1 all devices discontinued
lattice semiconductor ispgal22v10av/b/c data sheet 4 figure 5. logic diagram/jedec fuse map ?plcc & (qfn/qfns) package pinout 2 (30) 26 (25) olmc s1, s0 = 5810, 5811 sr = 5832 od = 5833 3 (31) asynchronous reset (to all registers) 0 jedec fuse #0 4 8 12 16 20 24 28 32 36 40 synchronous preset (to all registers) 12 (9) 27 (26) s1, s0 = 5808, 5809 sr = 5830 od = 5831 25 (24) olmc s1, s0 = 5812, 5813 sr = 5834 od = 5835 4 (32) 5 (1) 6 (2) 24 (23) olmc s1, s0 = 5814, 5815 sr = 5836 od = 5837 23 (22) olmc s1, s0 = 5816, 5817 sr = 5838 od = 5839 21 (19) olmc s1, s0 = 5818, 5819 sr = 5840 od = 5841 20 (18) olmc s1, s0 = 5820, 5821 sr = 5842 od = 5843 olmc s1, s0 = 5822, 5823 sr = 5844 od = 5845 10 (7) 19 (17) 18 (16) olmc s1, s0 = 5824, 5825 sr = 5846 od = 5847 11 (8) 17 (15) olmc s1, s0 = 5826, 5827 sr = 5848 od = 5849 9 (6) 7 (3) 13 (10) 16 (14) 8 10 14 16 12 12 16 14 10 8 olmc s1, s0 = arch control bits sr = slew rate bit od = open drain bit jedec fuse #131 jedec fuse #5676 jedec fuse #5807 all devices discontinued
lattice semiconductor ispgal22v10av/b/c data sheet 5 electronic signature an electronic signature (es) is provided in every ispgal22v10a device. it contains 32 bits of reprogrammable memory that can contain user-de?ed data. some uses include user id codes, revision numbers, or inventory con- trol. the signature data is always available to the user independent of the state of the security cell. ieee 1149.1 and ieee 1532 compliant usercode is supported. low power and power management the ispgal22v10a family is designed with high speed low power design techniques to offer both high speed and low power. with an advanced e 2 low power cell and no sense-ampli?rs (full cmos logic approach), the ispgal22v10a family offers fast pin-to-pin speeds, while simultaneously delivering low standby power without requiring any ?urbo bits or other traditional power-management schemes. i/o con?uration each output supports a variety of output standards dependent on the v cco . outputs can also be con?ured for open drain operation. each input can be programmed to support a variety of standards, independent of the v cco supplied to its i/o. for 28 plcc package the v cco and v cc must be the same. the option to set the v cco inde- pendent of v cc is available with the 32 qfn/qfns package only. the i/o standards supported are: lvttl lvcmos 1.8 lvcmos 3.3 3.3v pci compatible lvcmos 2.5 all of the i/os and dedicated inputs have the capability to provide a bus-keeper latch, pull-up resistor or pull-down resistor. a fourth option is to provide none of these. the selection is done on a global basis. the default in both hardware and software is such that when the device is erased or if the user does not specify, the input structure is con?ured to be a pull-up resistor. each ispgal22v10a device i/o has an individually programmable output slew rate control bit. each output can be individually con?ured for fast slew or slow slew. the typical edge rate difference between fast and slow slew set- ting is 20%. for high-speed designs with long, unterminated traces, the slow-slew rate will introduce fewer re?c- tions, less noise and keep ground bounce to a minimum. for designs with short traces or well terminated lines, the fast slew rate can be used to achieve the highest speed. ieee 1149.1-compliant boundary scan testability all ispgal22v10a devices have boundary scan cells and are compliant to the ieee 1149.1 standard. this allows functional testing of the circuit board on which the device is mounted through a serial scan path that can access all critical logic notes. internal registers are linked internally, allowing test data to be shifted in and loaded directly onto test nodes, or test node data to be captured and shifted out for veri?ation. in addition, these devices can be linked into a board-level serial scan path for more board-level testing. the test access port operates with an lvcmos interface that corresponds to the power supply voltage. ieee 1532-compliant in-system programming programming devices in-system provides a number of signi?ant bene?s including rapid prototyping, lower inven- tory levels, higher quality and the ability to make in-?ld modi?ations. all ispgal22v10a devices provide in-sys- tem programming (isp) capability through the boundary scan test access port. this capability has been implemented in a manner that ensures that the port remains complaint to the ieee 1149.1 standard. by using ieee 1149.1 as the communication interface through which isp is achieved, users get the bene? of a standard, well- de?ed interface. all ispgal22v10a devices are also compliant with the ieee 1532 standard. the ispgal22v10a devices can be programmed across the commercial temperature and voltage range. the pc- based lattice software facilitates in-system programming of ispgal22v10a devices. the software takes the jedec ?e output produced by the design implementation software, along with information about the scan chain, and creates a set of vectors used to drive the scan chain. the software can use these vectors to drive a scan chain all devices discontinued
lattice semiconductor ispgal22v10av/b/c data sheet 6 via the parallel port of a pc. alternatively, the software can output ?es in formats understood by common auto- mated test equipment. this equipment can then be used to program ispgal22v10a devices during the testing of a circuit board. security bit a programmable security bit is provided on the ispgal22v10a devices as a deterrent to unauthorized copying of the array con?uration patterns. once programmed, this bit defeats readback of the programmed pattern by a device programmer, securing proprietary designs from competitors. programming and veri?ation are also defeated by the security bit. the bit can only be reset by erasing the entire device. hot socketing the ispgal22v10a devices are well-suited for applications that require hot socketing. hot socketing a device requires that the device, during power-up and down, tolerate active signals on the i/os and inputs without being damaged. additionally, it requires that the effects of i/o pin loading be minimal on active signals. the ispgal22v10a devices provide this capability for input voltages in the range of 0v to 3.0v. power-up reset circuitry within the ispgal22v10a provides a reset signal to all registers during power-up. all internal registers will have their q outputs set low after a speci?d time (tpr, 1? typical). as a result, the state on the registered output pins (if they are enabled) will be either high or low on power-up, depending on the programmed polarity of the out- put pins. this feature can greatly simplify state machine design by providing a known state on power-up. the timing diagram for power-up is shown above. because of the asynchronous nature of system power-up, some conditions must be met to provide a valid power-up reset of the ispgal22v10a. first, the vcc rise must be monotonic. sec- ond, the clock input must be at static ttl level as shown in the diagram during power up. the registers will reset within a maximum of tpr time. as in normal system operation, avoid clocking the device until all input and feedback path setup times have been met. the clock must also meet the minimum pulse width requirements. figure 6. timing diagram for power-up vcc (min.) t pr internal register reset to logic "0" device pin reset to logic "1" t wl t su device pin reset to logic "0" vcc clk internal register q - output active low output register active high output register all devices discontinued
lattice semiconductor ispgal22v10av/b/c data sheet 7 absolute maximum ratings 1, 2, 3 ispgal ispgal ispgal 22v10ac (1.8v) 22v10ab (2.5v) 22v10av (3.3v) supply voltage v cc . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 2.5v -0.5 to 5.5v -0.5 to 5.5v output supply voltage v cco . . . . . . . . . . . . . . . . . -0.5 to 4.5v -0.5 to 4.5v -0.5 to 4.5v input or i/o tristate voltage applied 4 . . . . . . . . . . . -0.5 to 5.5v -0.5 to 5.5v -0.5 to 5.5v storage temperature . . . . . . . . . . . . . . . . . . . . . . . -65 to 150 c -65 to 150 c -65 to 150 c junction temperature (t j ) with power applied . . . . -55 to 150 c -55 to 150 c -55 to 150 c 1. stress above those listed under the ?bsolute maximum ratings may cause permanent damage to the device. functional operation of the device at these or any other conditions above those indicated in the operational sections of this speci?ation is not implied. 2. compliance with lattice thermal management document is required. 3. all voltages referenced to gnd. 4. undershoot of -2v and overshoot of (v ih (max) +2), up to a total pin voltage of 6.0v, is permitted for a duration of < 20ns. recommended operating conditions erase reprogram speci?ations hot socketing characteristics 1,2,3 i/o recommended operating conditions symbol parameter min max units v cc supply voltage for 1.8v devices 1.65 1.95 v supply voltage for 2.5v devices 2.3 2.7 v supply voltage for 3.3v devices 3.0 3.6 v t j junction temperature (commercial) 0 90 c junction temperature (industrial) -40 105 c parameter min max units erase/reprogram cycle 1,000 cycles note: valid over commercial temperature range. symbol parameter condition min typ max units i dk input or i/o leakage current 0 v in 3.0v, t j = 105? ?0 a 1. insensitive to sequence of v cc and v cco . however, assumes monotonic rise/fall rates for v cc and v cco , provided (v in - v cco ) 3.0v. 2. 0 v cc v cc (max), 0 v cco v cco (max) 3. i dk is additive to i pu , i pd or i bh . device defaults to pull-up until fuse circuitry is active. standard v cco (v) 1 min max lvttl 3.0 3.6 lvcmos 3.3 3.0 3.6 lvcmos 2.5 2.3 2.7 lvcmos 1.8 1.65 1.95 pci 3.3 3.0 3.6 1. typical values for v cco are the average of the min and max values. all devices discontinued
lattice semiconductor ispgal22v10av/b/c data sheet 8 dc electrical characteristics over recommended operating conditions symbol parameter condition min typ max units i il , i ih 1 input leakage current 0 < v in 3.6v, t j = 105? 10 ? i ih 2 input high leakage current 3.6v < v in 5.5v, t j = 105? 3.0v v cco 3.6v 20 ? i os output short circuit current v cc = 3.3v, v out = 0.5v, t a = 25? -80 ma i pu i/o weak pull-up resistor current 0 v in 0.7v cco 20 150 ? i pd i/o weak pull-down resistor current v il (max) v in v ih (max) 20 150 ? i bhls bus hold low sustaining current v in = v il (max) 20 ? i bhhs bus hold high sustaining current v in = 0.7 v cco 20 ? i bhlo bus hold low overdrive current 0v v in v ih (max) 150 ? i bhho bus hold high overdrive current 0 v in v ih (max) 150 ? v bht bus hold trip points v il (max) v ih (min) v c 1 i/o capacitance 3 v cco = 3.3v, 2.5v, 1.8v 6 pf v cc = 1.8v, v io = 0 to v ih (max) c 2 clock capacitance 3 v cco = 3.3v, 2.5v, 1.8v 8 pf v cc = 1.8v, v io = 0 to v ih (max) 1. input or i/o leakage current is measured with the pin con?ured as an input or as an i/o with the output driver tristated. it is not measured with the output driver active. bus maintenance circuits are disabled. 2. 5 volt tolerant inputs and i/os apply to v cco condition of 3.0v v cco 3.6v. 3. t a = 25?, frequency = 1.0mhz supply current over recommended operating conditions symbol parameter condition min typ max units ispgal22v10av/b/c i cc 1, 2 operating power supply current v cc = 3.3v 8 90 ma v cc = 2.5v 8 90 ma v cc = 1.8v 3 80 ma i cc 3 standby power supply current v cc = 3.3v 7 ma v cc = 2.5v 7 ma v cc = 1.8v 150 ? 1. t a = 25 c, frequency = 15mhz. 2. i cc varies with speci? device con?uration and operating frequency. 3. t a = 25c all devices discontinued
lattice semiconductor ispgal22v10av/b/c data sheet 9 i/o dc electrical characteristics 1 over recommended operating conditions standard v il v ih v ol max (v) v oh min (v) i ol (ma) i oh (ma) min (v) max (v) min (v) max (v) lvttl -0.3 0.80 2.0 5.5 0.40 v cco - 0.40 8.0 -4.0 0.20 v cco - 0.20 0.1 -0.1 lvcmos 3.3 -0.3 0.80 2.0 5.5 0.40 v cco - 0.40 8.0 -4.0 0.20 v cco - 0.20 0.1 -0.1 lvcmos 2.5 -0.3 0.70 1.70 3.6 0.40 v cco - 0.40 8.0 -4.0 0.20 v cco - 0.20 0.1 -0.1 lvcmos 1.8 (ispgal22v10av/b) -0.3 0.63 1.17 3.6 0.40 v cco - 0.45 2.0 -2.0 0.20 v cco - 0.20 0.1 -0.1 lvcmos 1.8 (ispgal22v10ac) -0.3 0.35 v cc 0.65 * v cc 3.6 0.40 v cco - 0.45 2.0 -2.0 0.20 v cco - 0.20 0.1 -0.1 pci 3.3 (ispgal22v10av/b) -0.3 1.08 1.5 5.5 0.1 v cco 0.9 v cco 1.5 -0.5 pci 3.3 (ispgal22v10ac) -0.3 0.3 * 3.3 * (v cc / 1.8) 0.5 * 3.3 * (v cc / 1.8) 5.5 0.1 v cco 0.9 v cco 1.5 -0.5 1. for 28 plcc package the i/o voltage and core voltage must be the same. the option to set the i/o voltage independent of the core voltage is available with the 32 qfn/qfns package only. v o output voltage (v) typical i/o output current (ma) 3.3v v cco v o output voltage (v) 0 0 0 20 40 60 80 100 10 20 30 40 50 60 0 10 20 30 40 50 60 70 2.0 1.5 1.0 0.5 0 2.0 2.5 3.0 3.5 1.51.00.5 02 . 0 2 . 5 1.51.00.5 typical i/o output current (ma) 1.8v v cco v o output voltage (v) i oh typical i/o output current (ma) 2.5v v cco i ol i oh i ol i oh i ol all devices discontinued
lattice semiconductor ispgal22v10av/b/c data sheet 10 ispgal22v10av/b/c external switching characteristics 1 over recommended operating conditions param description -23 -28 -5 -75 units min max min max min max min max t pd 1 output switching propagation delay 2.3 2.8 ns 10 output switching propagation delay 2.6 3.0 5.0 7.5 t co clock to output delay 2.0 2.5 3.5 5.0 ns t cf 2 clock to feedback delay 1.9 2.2 2.5 2.5 ns t su setup time, input or feedback before clk 1.3 2.0 3.5 5.0 ns t h hold time, input or feedback after clk 0???ns f max 3 maximum clock frequency with external feedback, [1/ (t su + t co )] 303 222 143 100 ns maximum clock frequency with internal feedback, [1/ (t su + t cf )] 312 238 166 133 ns maximum clock frequency with no feedback 455 357 200 166 ns t wh 3 clock pulse duration, high 1.1 1.4 2.5 3.0 ns t wl 3 clock pulse duration, low 1.1 1.4 2.5 3.0 ns t en input or i/o to output enabled 3.0 3.5 6.0 7.5 ns t dis input or i/o to output disabled 3.0 3.5 6.0 7.5 ns t ar input or i/o to asynch, reset of reg. 2.8 3.5 5.5 9.0 ns t arw asysnchronous reset pulse duration 2.8 3.5 5.5 7.0 ns t arr asysnchronous reset to clk recovery time 2.5 3.0 4.0 5.0 ns t spr synchronous preset to clk recovery time 2.5 3.0 4.0 5.0 ns 1. refer to switching test conditions section. 2. calculated from fmax with internal feedback. refer to fmax descriptions section. 3. refer to fmax descriptions section. characterized but not 100% tested. note: maximum clock input rise and fall time between 10% to 90% of vout = 2ns. all devices discontinued
lattice semiconductor ispgal22v10av/b/c data sheet 11 ispgal22v10av/b/c timing adders over recommended operating conditions adder type description -23 -28 -5 -75 units min. max. min. max. min. max. min. max. t ioi input adjusters lvttl_in using lvttl standard 0.6 0.6 0.6 0.6 ns lvcmos33_in using lvcmos 3.3 standard 0.6 0.6 0.6 0.6 ns lvcmos25_in using lvcmos 2.5 standard 0.6 0.6 0.6 0.6 ns lvcmos18_in using lvcmos 1.8 standard ??? 0ns pci_in using pci compatible input 0.6 0.6 0.6 0.6 ns t ioo output adjusters lvttl_out output con?ured as ttl buffer 0.2 0.2 0.2 0.2 ns lvcmos33_out output con?ured as 3.3v buffer 0.2 0.2 0.2 0.2 ns lvcmos25_out output con?ured as 2.5v buffer 0.1 0.1 0.1 0.1 ns lvcmos18_out output con?ured as 1.8v buffer 0 ?? 0ns pci_out output con?ured as pci compatible buffer 0.2 0.2 0.2 0.2 ns slow slew output con?ured for slow slew rate 1.0 1.0 1.0 1.0 ns note: open drain timing is the same as corresponding lvcmos timing. all devices discontinued
lattice semiconductor ispgal22v10av/b/c data sheet 12 switching waveforms figure 7. ispgal22v10av/b/c switching waveforms input or i/o feedback registered output clk valid input t su t co t h (external fdbk) 1/ f max valid input input or i/o feedback t pd combinatorial output clk registered feedback t cf t su 1/ f max (internal fdbk) clk (w/o fdbk) t wh t wl 1/ f max registered output clk t arw t arr input or i/o feedback driving ar t ar registered output clk input or i/o feedback driving sp t su t h t co t spr t en t dis input or i/o feedback output combinatorial output registered output input or i/o to output enable/disable f max with feedback synchronous preset clock width asynchronous reset all devices discontinued
lattice semiconductor ispgal22v10av/b/c data sheet 13 f max descriptions figure 8. ispgal22v10av/b/c f max descriptions register logic array t co t su clk register logic array clk t su + t h clk register logic array t cf t pd note: tcf is a calculated value, derived by subtracting tsu from the period of fmax w/internal feedback (tcf = 1/fmax - tsu). the value of tcf is used primarily when calculating the delay from clocking a register to a combinatorial output (through registered feedback), as shown above. for example, the timing from clock to a combinatorial output is equal to tcf + tpd. note: fmax with external feedback is calculated from measured tsu and tco. note: fmax with no feedback may be less than 1/twh + twl. this is to allow for a clock duty cycle of other than 50%. fmax with internal feedback 1/(tsu+tcf) fmax with external feedback 1/(tsu+tco) fmax with no feedback all devices discontinued
lattice semiconductor ispgal22v10av/b/c data sheet 14 switching test conditions figure 9 shows the output test load that is used for ac testing. the speci? values for resistance, capacitance, volt- age, and other test conditions are shown in table 1. figure 9. output test load, lvttl and lvcmos standards table 1. test fixture required components pin diagrams test condition i/o standard r 1 r 2 c l 1 input timing ref. 2 output timing ref. v cco lvcmos i/o, (l -> h, h -> l) lvcmos 3.3 106 106 35pf 1.5v 1.5v 3.0v lvcmos 2.5 1.2v v cco /2 2.3v lvcmos 1.8 (v/b) 0.9v v cco /2 (v/b) 1.65v (c) v cc /2 v cco /2 (c) v cc lvcmos i/o (z -> h) 106 106 35pf hi-z + 0.3 3.0v lvcmos i/o (z -> l) 106 106 35pf hi-z - 0.3 3.0v lvcmos i/o (h -> z) 106 5pf v oh - 0.3 3.0v lvcmos i/o (l -> z) 106 ? 5pf v ol + 0.3 3.0v 1. c l includes test ?tures and probe capacitance. 2. input conditions. v cco r 1 r 2 c l dut test point 228 tck i/clk i i i i i i i i tms tdo tdi gnd i i i i/o i/o i/o i/o i/o i/o i/o vcc i/o i/o i/o 42 6 25 19 18 21 23 16 14 12 11 9 7 5 top view plcc 29 28 tck i/clk i i i i i vcco i i tms tdo gndo gnd i i tdi i/o i i/o i i/o i/o gndo top view qfn, qfns i/o i/o i/o vcc i/o i/o i/o vcco 32 25 24 17 16 20 21 1312 9 8 5 4 1 all devices discontinued
lattice semiconductor ispgal22v10av/b/c data sheet 15 part number description ordering information conventional packaging commercial part number voltage t pd power package pin count grade ispgal22v10av-23ls 3.3 2.3ns low qfns 32 c ISPGAL22V10AV-23LN 1 3.3 2.3ns low qfn 32 c ispgal22v10av-5ls 3.3 5.0ns low qfns 32 c ispgal22v10av-5ln 1 3.3 5.0ns low qfn 32 c ispgal22v10av-75ls 3.3 7.5ns low qfns 32 c ispgal22v10av-75ln 1 3.3 7.5ns low qfn 32 c ispgal22v10av-28lj 3.3 2.8ns low plcc 28 c ispgal22v10av-5lj 3.3 5.0ns low plcc 28 c ispgal22v10av-75lj 3.3 7.5ns low plcc 28 c ispgal22v10ab-23ls 2.5 2.3ns low qfns 32 c ispgal22v10ab-23ln 1 2.5 2.3ns low qfn 32 c ispgal22v10ab-5ls 2.5 5.0ns low qfns 32 c ispgal22v10ab-5ln 1 2.5 5.0ns low qfn 32 c ispgal22v10ab-75ls 2.5 7.5ns low qfns 32 c ispgal22v10ab-75ln 1 2.5 7.5ns low qfn 32 c ispgal22v10ab-28lj 2.5 2.8ns low plcc 28 c ispgal22v10ab-5lj 2.5 5.0ns low plcc 28 c ispgal22v10ab-75lj 2.5 7.5ns low plcc 28 c ispgal22v10ac-23ls 1.8 2.3ns low qfns 32 c ispgal22v10ac-23ln 1 1.8 2.3ns low qfn 32 c ispgal22v10ac-5ls 1.8 5.0ns low qfns 32 c ispgal22v10ac-5ln 1 1.8 5.0ns low qfn 32 c ispgal22v10ac-75ls 1.8 7.5ns low qfns 32 c ispgal22v10ac-75ln 1 1.8 7.5ns low qfn 32 c ispgal22v10ac-28lj 1.8 2.8ns low plcc 28 c ispgal22v10ac-5lj 1.8 5.0ns low plcc 28 c ispgal22v10ac-75lj 1.8 7.5ns low plcc 28 c 1. use qfns package. qfn package devices have been discontinued via pcn #13a-08. device number ispgal 22v10a x ?xx x x x supply voltage v = 3.3v b = 2.5v c = 1.8v speed 23 = 2.3ns 28 = 2.8ns 5 = 5.0ns 75 = 7.5ns package j = plcc (28 pins) n = qfn (32 pins) nn = lead free qfn (32 pins) s = qfns (32 pins) sn = lead free qfns (32 pins) grade c = commercial i = industrial device family power l = low power all devices discontinued
lattice semiconductor ispgal22v10av/b/c data sheet 16 lead-free packaging note: for all but the slowest commercial speed grade, the speed grades on these devices are dual marked. for example, the commercial speed grade -5lj is also marked with the industrial grade -7lji. the commercial grade is always one speed grade faster than the associated dual mark industrial grade. the slowest commercial speed grade is marked as commercial grade only. industrial part number voltage t pd power package pin count grade ispgal22v10av-5lsi 3.3 5.0ns low qfns 32 i ispgal22v10av-5lni 1 3.3 5.0ns low qfn 32 i ispgal22v10av-75lsi 3.3 7.5ns low qfns 32 i ispgal22v10av-75lni 1 3.3 7.5ns low qfn 32 i ispgal22v10av-5lji 3.3 5.0ns low plcc 28 i ispgal22v10av-75lji 3.3 7.5ns low plcc 28 i ispgal22v10ab-5lsi 2.5 5.0ns low qfns 32 i ispgal22v10ab-5lni 1 2.5 5.0ns low qfn 32 i ispgal22v10ab-75lsi 2.5 7.5ns low qfns 32 i ispgal22v10ab-75lni 1 2.5 7.5ns low qfn 32 i ispgal22v10ab-5lji 2.5 5.0ns low plcc 28 i ispgal22v10ab-75lji 2.5 7.5ns low plcc 28 i ispgal22v10ac-5lsi 1.8 5.0ns low qfns 32 i ispgal22v10ac-5lni 1 1.8 5.0ns low qfn 32 i ispgal22v10ac-75lsi 1.8 7.5ns low qfns 32 i ispgal22v10ac-75lni 1 1.8 7.5ns low qfn 32 i ispgal22v10ac-5lji 1.8 5.0ns low plcc 28 i ispgal22v10ac-75lji 1.8 7.5ns low plcc 28 i 1. use qfns package. qfn package devices have been discontinued via pcn #13a-08. commercial part number voltage t pd power package pin count grade ispgal22v10av-23lsn 3.3 2.3ns low qfns 32 c ISPGAL22V10AV-23LNn 1 3.3 2.3ns low qfn 32 c ispgal22v10av-5lsn 3.3 5.0ns low qfns 32 c ispgal22v10av-5lnn 1 3.3 5.0ns low qfn 32 c ispgal22v10av-75lsn 3.3 7.5ns low qfns 32 c ispgal22v10av-75lnn 1 3.3 7.5ns low qfn 32 c 1. use qfns package. qfn package devices have been discontinued via pcn #13a-08. industrial part number voltage t pd power package pin count grade ispgal22v10av-5lsni 3.3 5.0ns low qfns 32 i ispgal22v10av-5lnni 1 3.3 5.0ns low qfn 32 i ispgal22v10av-75lsni 3.3 7.5ns low qfns 32 i ispgal22v10av-75lnni 1 3.3 7.5ns low qfn 32 i 1. use qfns package. qfn package devices have been discontinued via pcn #13a-08. all devices discontinued
lattice semiconductor ispgal22v10av/b/c data sheet 17 revision history date version change summary previous lattice releases. december 2008 03.0 added 32-pin qfns package ordering part number information per pcn #13a-08. all devices discontinued

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